Working at STT

Spin Transfer Technologies (STT) is focused on the development of novel magnetoresistive random access memory (MRAM) technologies and devices in collaboration with New York University researchers and industry partners.

STT is an equal opportunity employer offering competitive benefits.

Positions

Description

As the leader of our CAD automation team, you will be responsible for developing and enhancing Front-end and Back-end flows in a custom IC environment. You will develop and support flows for analog and digital design environments, automation of flows for digital simulation, DFT capabilities, synthesis, equivalence checking, P&R, physical verification, timing closure, and power sign-off and chip tapeouts.

You will manage projects and give guidance and support on the various EDA tools working closely with experienced designers and CAD engineers to ensure successful design completion. You should be able to analyze complex technical issues, address them in a clear fashion with EDA vendors and follow up with the users and management on the status of the issues. You must stay current with new developments from EDA vendors.

Qualifications

Candidate should possess a Bachelor or Master of Science degree + 10 years of relevant industry experience in a chip design environment:

  • Significant experience leading small teams of engineers
  • Thorough knowledge of memory, logic and analog design methodologies
  • Familiarity with schematic and layout design and simulation methodology
  • Hands-on experience with industry-standard EDA tools from Cadence, Synopsys and Mentor, such as Encounter, IC Compiler, Design Compiler, Calibre, Virtuoso etc.
  • Strong programming skills in C/C++, Python, Perl, tcl, awk, shell scripting, etc.
  • Self-motivated, able to work independently or as a team player
  • Excellent interpersonal, verbal and written communication skills

Submit your resume to: careers@spintransfer.com

Description

You will be responsible for leading both internal and outsourced layout development activity for logic and MRAM circuitry. You will direct cell, block, and array layout activities for library and full chip projects. Activities will include interfacing with multi-discipline design teams, develop schedule timelines for layout execution and leading your team to implement it, skill development to grow the capabilities of your Physical Design team, developing and implementing methodology improvements to ensure better efficiency and effectiveness, making in-house versus outsource recommendations.

Qualifications

Candidate should have 10+ years of directly relevant layout and leadership experience. Bachelor of Science degree a plus.

  • Demonstrated leadership skills with a strong background in layout
  • Extensive experience in Full Chip layout planning & assembly with a background in memory layout, arrays and hierarchy
  • Thorough knowledge of layout of Analog/Mixed signal circuit blocks and the physical layout requirements
  • Extensive experience in performing DRC/LVS/ERC/Antenna EM and IR analysis and other checks, R&C extraction for different layout levels
  • Ability to generate LEF’s for use by customers
  • Must have strong skills in layout, floor planning, and manual routing
  • Strong understanding of device optimization, component matching, minimizing parasitics, including techniques to minimize manufacturing variations
  • Knowledge of semiconductor wafer fabrication steps to support layout development using proper CAD layers
  • Knowledge of Cadence and Mentor Graphics tools
  • A self-starter who is pro-active, a fast learner, detail oriented, and team oriented

Submit your resume to: careers@spintransfer.com

Description

You will be responsible for creating, defining, documenting and communicating innovative solutions that enable efficient and effective testing and debug of MRAM chips as they move from prototype to production. As a regular part of your daily job you will be exposed to multiple disciplines of chip development including RTL/Logic design, Verification, Validation, Physical Design, Silicon Engineering and operations teams. You will drive testability in areas ranging from design validation to improving yield focused on providing high quality production chips. You will be a major contributor to the RTL-level and gate-level verification efforts for the memory BIST, Logic BIST, JTAG, and Boundary scan logic for a family of products.

Qualifications

Candidate should possess a Bachelor or Master of Science degree in Computer or Electrical Engineering with 5+ years of directly relevant experience:

  • Deep understanding and hands on experience implementing memory BIST, Logic BIST, Serdes and IO test, JTAG, and boundary scan logic
  • Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power and high performance design techniques
  • Hands on experience in logic synthesis and integrating RTL driven logic into the full chip
  • Hands on experience in integrating acquired IP blocks into a synthesized design
  • Extensive experience supporting operational teams on silicon bring-up and yield improvement including pattern generation and debug, failure analysis, ATPG diagnostic flow automation
  • Familiarity with FPGA emulation techniques
  • Experience in C or C++ programming and other scripting languages such as Perl or Python

Submit your resume to: careers@spintransfer.com

Description

You will own or participate in the definition, design, verification, and documentation for digital logic systems on integrated circuits. This includes developing architecture, module interfaces, and design approaches used in creating logic designs, Register Transfer Level models, and simulating functional units and subsystems included in the development of complex multidimensional designs.

  • Architecture and Definitions: Converting customer and product requirements into detailed design goals to be used in implementation
  • RTL ownership: Development, assessment and refinement of RTL design to target power, performance, area and timing goals
  • Validation: Support test-bench development and simulation for functional and performance verification
  • Performance exploration and correlation: Explore high performance strategies and validate that the RTL design meets targeted performance
  • Design delivery: Work with cross-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power

Qualifications

Candidate should possess a Bachelor or Master of Science degree in Computer or Electrical Engineering with 5+ years of directly relevant experience:

  • Thorough knowledge of chip architecture
  • Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power design techniques
  • Understanding of high performance techniques and trade-offs
  • Hands on experience in logic synthesis and integrating RTL driven logic into the full chip
  • Hands on experience in integrating acquired IP blocks into a synthesized design
  • Familiarity with FPGA emulation techniques
  • Experience in C or C++ programming and other programming languages such as Perl or Python
  • Ability to generate library models (.lib) for embedded macro use
  • Ability to generate memory BIST models for use with MBIST tools
  • Experience with memory BIST generation and usage for embedded macros
  • Ability to generate Verilog models for use by customers in their simulation environment

Submit your resume to: careers@spintransfer.com

Description

As a member of our MRAM design team you will develop custom analog circuits for a variety of new MRAM memory devices. You will design, model, and verify critical custom circuits used in our MRAM memory devices. In the design phase you will also oversee the circuit layout and verify post-layout performance as well as integration into the full chip-level assembly. During design validation you will drive the analysis of the blocks you designed. This position requires demonstrated custom analog design experience.

Qualifications

Candidate should possess a Bachelor or Master of Science degree in Electrical Engineering with 5+ years of directly relevant experience in custom IC circuit design:

  • Significant recent experience with analog design, circuit verification and optimization
  • Experience with layout floor-planning
  • Significant experience with verification of parasitic extractions of the circuits
  • Proficiency performing analog, mixed signal, and co-sim simulations using standard industry simulators
  • Experience with Cadence analog design flow with tools such as Hspice, Spectre, HSIM, Ultrasim, XA
  • Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
  • Experience with multi-gigabit CMOS technology
  • Timing generator, bandgap circuit design, current and voltage reference generation, operational amplifier circuits, and sense amplifier circuits experience is a plus
  • Demonstrate a high level of self-motivation

Submit your resume to: careers@spintransfer.com