Working at STT

Spin Transfer Technologies (STT) is focused on the development of novel magnetoresistive random access memory (MRAM) technologies and devices in collaboration with New York University researchers and industry partners.

STT is an equal opportunity employer offering competitive benefits.

Positions

Description

You will be responsible for leading both internal and outsourced layout development activity for logic and MRAM circuitry. You will direct cell, block, and array layout activities for library and full chip projects. Activities will include interfacing with multi-discipline design teams, develop schedule timelines for layout execution and leading your team to implement it, skill development to grow the capabilities of your Physical Design team, developing and implementing methodology improvements to ensure better efficiency and effectiveness, making in-house versus outsource recommendations.

Qualifications

Candidate should have 10+ years of directly relevant layout and leadership experience. Bachelor of Science degree a plus.

  • Demonstrated leadership skills with a strong background in layout
  • Extensive experience in Full Chip layout planning & assembly with a background in memory layout, arrays and hierarchy
  • Thorough knowledge of layout of Analog/Mixed signal circuit blocks and the physical layout requirements
  • Extensive experience in performing DRC/LVS/ERC/Antenna EM and IR analysis and other checks, R&C extraction for different layout levels
  • Ability to generate LEF’s for use by customers
  • Must have strong skills in layout, floor planning, and manual routing
  • Strong understanding of device optimization, component matching, minimizing parasitics, including techniques to minimize manufacturing variations
  • Knowledge of semiconductor wafer fabrication steps to support layout development using proper CAD layers
  • Knowledge of Cadence and Mentor Graphics tools
  • A self-starter who is pro-active, a fast learner, detail oriented, and team oriented

Submit your resume to: careers@spintransfer.com

Description

As a member of our MRAM design team you will develop custom analog circuits for a variety of new MRAM memory devices. You will design, model, and verify critical custom circuits used in our MRAM memory devices. In the design phase you will also oversee the circuit layout and verify post-layout performance as well as integration into the full chip-level assembly. During design validation you will drive the analysis of the blocks you designed. This position requires demonstrated custom analog design experience.

Qualifications

Candidate should possess a Bachelor or Master of Science degree in Electrical Engineering with 5+ years of directly relevant experience in custom IC circuit design:

  • Significant recent experience with analog design, circuit verification and optimization
  • Experience with layout floor-planning
  • Significant experience with verification of parasitic extractions of the circuits
  • Proficiency performing analog, mixed signal, and co-sim simulations using standard industry simulators
  • Experience with Cadence analog design flow with tools such as Hspice, Spectre, HSIM, Ultrasim, XA
  • Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form
  • Experience with multi-gigabit CMOS technology
  • Timing generator, bandgap circuit design, current and voltage reference generation, operational amplifier circuits, and sense amplifier circuits experience is a plus
  • Demonstrate a high level of self-motivation

Submit your resume to: careers@spintransfer.com

Description

  • Process Owner for CMP process including development, SPC strategy, materials selection (i.e. Pad, Slurry, etc.) and evaluation.
  • Perform CMP related processes including cleaner and spin rinse dryer.
  • Perform post process metrology including microscope inspection and AFM, ellipsometry.

Submit your resume to: careers@spintransfer.com